1. Field of the Invention
The present invention relates to a ball grid array (BGA) package. In particular, the present invention discloses a BGA package with a same power ballout assignment for the wire bonding packaging and the flip chip packaging.
2. Description of the Prior Art
In modern society with developed computer technology, the computer system, which comprises a plurality of integrated circuits, has been utilized in a broad spectrum of fields. For example, household appliances with automatic control systems, mobile communication devices, and personal computers utilize integrated circuits to perform certain functions. Therefore, integrated circuits exist everywhere around the world. The main body of the IC is a die manufactured by a prior art semiconductor process. The manufacturing process of the die starts from forming a wafer. Each wafer is divided into a plurality of regions. On each region, many circuits are formed through the prior art semiconductor process. In the end, each processed region on the wafer is sliced to generate a plurality of dies. After the required die is obtained, it requires a specific way to electrically connect the processed die with a circuit board such as a printed circuit board (PCB). Therefore, the die is capable of acquiring its operating voltage from the PCB for performing a predetermined operation. For instance, suppose that the die corresponds to an encoder circuit. After the encoder circuit is provided with an appropriate operating voltage, the die (encoder circuit) is capable of encoding data inputted from the circuit board, and then returns the encoded data to the circuit board. Generally speaking, the specific way for electrically connecting the die with the circuit board comprises connecting a bare chip (die) directly with the circuit board, or packaging the die inside a package in advance so that the die is electrically connected to the outer circuit board through a circuit layout within the package for receiving power and transmitting signals.
The main purpose of the package is to provide a signal transmission interface between the die and the corresponding circuit board and a protective shield for the interior die. In addition, current electric appliances are developed to have a smaller size and a greater processing speed. Therefore, the package needs to increase a desired package pincount number, and simultaneously reduce the thickness and the area to meet user's requirement. In the past, the pin through hole (PTH) technology is particularly restricted by size of the holes that are positioned on the circuit board. Therefore, the actual size of the package cannot be greatly reduced owing to its inborn limitation. In addition, the package pincount number is accordingly restricted. Consequently, the surface mount technology (SMT) replaces the PTH technology to reduce actual size of the package. However, the above-mentioned surface mount technology and pin through hole technology belong to a peripheral packaging category. The peripheral packaging method has its own constitutional limitation on downsizing the package and increasing the package pincount number. Taking the SMT for example, when the total number of the pins located at peripheral of the package increases, the pitch between adjacent pins is accordingly shortened. When the package is installed upon the corresponding circuit board, the yield of the assembly, therefore, is deteriorated because the pitch between adjacent pins is too narrow. Therefore, an area array packaging technology such as a ball grid array (BGA) package is developed to solve the above problem. The package pins are not located at a peripheral of the package, but are located at an area of the package. Not only is the pitch between adjacent pins widened to improve yield of the assembly, but also the package pincount number is greatly increased. Based on different electrical connections for the die, the BGA packages are categorized into a wire bonding BGA package and a flip chip BGA package.
Please refer to FIG. 1, which is a first diagram of a prior art wire bonding BGA package 10. The BGA package 10 has a die 11 and a substrate 12. The die 11 includes a core circuit 13 used for performing a predetermined operation, a plurality of input/output circuits 14a, 14b, 14c used for controlling signals inputted into the core circuit 13 and signals outputted from the core circuit 13, and a plurality of bonding pads 18 used for connecting the die 11 and the substrate 12. The substrate has a plurality of power rings 20a, 20b, 20c, 20d for carrying different operating voltages, and a plurality of solder joints 22. Besides, the power rings 20a, 20b, 20c and the solder joints 22 are both positioned on the same first layout layer 28. For example, suppose that the package 10 is a north bridge chip within a computer system. The die 11 is used to control signal transmission between high-speed peripheral devices (a memory and a graphics card for instance) and a microprocessor (a central processing unit (CPU) for instance). That is, the core circuit 13 of the die 11 dominates the kernel operation. On the other hand, the input/output circuits 14a, 14b, 14c, are respectively used to control signal transmission between the core circuit 13 and the memory, the graphics card, and the CPU. Please note that operating voltages of the memory, the graphics card, and the CPU are different to each other. For example, the memory needs an operating voltage equaling 2.6V, the graphics card using an accelerated graphics port (AGP) needs an operating voltage equaling 1.5V, and the CPU needs an operating voltage equaling 1.2V. That is, the memory uses 2.6V to represent a high logic value “1”, and uses a ground voltage (0V) to stand for a low logic value “0”. Therefore, the corresponding input/output circuit 14a has to use an operating voltage equaling 2.6V for correctly detecting logic values of a signal inputted from the memory and assigning logic values to a signal outputted to the memory. Similarly, the input/output circuit 14b has to use an operating voltage equaling 1.5V for correctly detecting logic values of a signal inputted from the graphics card and assigning logic values to a signal outputted to the graphics card, and the input/output circuit 14c has to use an operating voltage equaling 1.2V for correctly detecting logic values of a signal inputted from the CPU and assigning logic values to a signal outputted to the CPU. In addition, the core circuit 13 has an operating voltage different from that of each input/output circuit 14a, 14b, or 14c. The substrate 12, therefore, has to provide the core circuit 13 with an appropriate voltage such as 2.5V. The power rings 20a, 20b, 20c, 20d are respectively used to provide the input/output circuits 14a, 14b, 14c and the core circuit 13 with required operating voltages. It is noteworthy that bonding pads 18 corresponding to the input/output circuits 14a, 14b, 14c and the core circuit 13 are capable of transmitting signals and operating voltages. In FIG. 1, bonding wires 16a, 16b, 16c, 16d are used to connect the bonding pads 18 with the power rings 20a, 20b, 20c, 20d for individually inputting operating voltages into the input/output circuits 14a, 14b, 14c and the core circuit 13. Besides, bonding wire 16e is electrically connected between the bonding pad 18 and the corresponding solder joint 22 for transmitting signals. Every connection between the bonding wires and corresponding solder joints are not shown in FIG. 1 for simplicity. With the help of the bonding wires 16a, 16b, 16c, 16d, 16e, the die 11 can acquire desired operating voltages from the substrate 12, and the die 11 and the substrate 12 can transmit signals to each other.
Please refer to FIG. 2 in conjunction with FIG. 3. FIG. 2 is a second diagram of the wire bonding BGA package 10 shown in FIG. 1, and FIG. 3 is a section view along line 3–3″ of the wire bonding BGA package 10 shown in FIG. 1. The BGA package 10 has a plurality of ballouts 24 that are located at a second layout layer 30 according to a matrix format. The second layout layer 30 includes a plurality of conductive blocks 26a, 26b, 26c, 26d. Ballouts 24 positioned at each conductive block 26a, 26b, 26c, 26d are electrically connected to a circuit board that is used for inputting appropriate operating voltages to the input/output circuits 14a, 14b, 14c and the core circuit 13. As shown in FIG. 3, the first layout layer 28 and the second layout layer 30 are individually positioned at a top surface and a bottom surface of the BGA package 10. Please note that both FIG. 1 and FIG. 2 are top views so that the conductive blocks 26a, 26b, 26c, 26d and corresponding power rings 20a, 20b, 20c, 20d are capable of being electrically connected through vias 32. When the BGA package 10 is installed onto a circuit board through solder balls 34 at its bottom, the ballouts 24 corresponding to the solder balls 34 are electrically connected to the circuit board. Therefore, when the circuit board inputs voltages, the inputted voltages drive the input/output circuit 14a, 14b, 14c and the core circuit 13 through the solder balls 34, ballouts 24, vias 32, power rings 20a, 20b, 20c, 20d, bonding wires 16a, 16b, 16c, 16d, and bonding pads 18. Similarly, when the circuit board inputs signals into the input/output circuits 14a, 14b, 14c, the signals are transmitted to the input/output circuit 14a, 14b, 14c through the solder balls 34, ballouts 24, vias 32, solder joints 22, bonding wires 16e, and bonding pads 18. When the input/output circuits 14a, 14b, 14c outputs signals to the circuit board, the signals are transmitted through the bonding pads 18, bonding wires 16e, solder joints 22, vias 32, ballouts 24, and solder balls 34.
Please refer to FIG. 4, FIG. 5, and FIG. 6. FIG. 4 is a first diagram of a prior art flip chip BGA package 40. FIG. 5 is a second diagram of the flip chip BGA package 40 shown in FIG. 4. FIG. 6 is a section view along line 6–6″ of the flip chip BGA package 40 shown in FIG. 1. The BGA package 40 has a die 41 and a substrate 42. The die 41 includes a core circuit 43 and a plurality of input/output circuits 44a, 44b, 44c. The substrate 42 has a plurality of power rings 50a, 50b, 50c, 50d used for carrying different operating voltages, and the power rings 50a, 50b, 50c, 50d are positioned at the same first layout layer 58. Operation of the core circuit 43, the input/output circuits 44a, 44b, 44c, and power rings 50a, 50b, 50c, 50d is identical to the same elements of the above-mentioned wire bonding BGA package 10. Therefore, the lengthy description is skipped for simplicity. As shown in FIG. 5, the BGA package 40 has a plurality of ballouts 54 located at a second layout layer 60 according to a matrix format. The second layout layer 60 has a plurality of conductive blocks 56a, 56b, 56c, 56d. The ballouts 54 located at each conductive block 56a, 56b, 56c, 56d are used to connect a circuit board that is capable of providing the input/output circuits 44a, 44b, 44c and the core circuit 43 with appropriate operating voltages. The major difference between the flip chip BGA package 40 and the wire bonding BGA package 10 is that the die 41 is mounted by flipping over the die 11 shown in FIG. 1. In other words, the bonding pads 18 shown in FIG. 3 are located at top surface of the die 11, but the bonding pads 48 shown in FIG. 6 are located at bottom surface of the die 41. In addition, there is a metal bump 66 such as a solder bump or a gold bump formed on each bonding pad 48 so as to connect the corresponding contact 68 on the first layout layer 58 of the substrate 42. The power rings 50a, 50b, 50c, 50d and the contacts 68 (the first layout layer 58) are electrically connected to a third layout layer 70 through vias 62. With an adequate trace design for the third layout layer 70, the power rings 50a, 50b, 50c, 50d can transfer operating voltages to the core circuit 43 and the input/output circuits 44a, 44b, 44c through the corresponding contacts 68. Similarly, the third layout layer 70 is electrically connected to the second layout layer 60 through vias 62. Therefore, vias 62 can used to transmit signals and voltages to the die 41. Like the wire bonding BGA package 10, the flip chip BGA package 40 also adopts solder balls 64 to connect the circuit board.
Please refer to FIG. 1 in conjunction with FIG. 4. The wire bonding BGA package 10 and the flip chip BGA package 40 correspond to different power ring configurations. With regard to the wire bonding BGA package 10, the power rings 20a, 20b, 20c corresponding to the input/output circuits 14a, 14b, 14c are positioned inside the power ring 20d corresponding to the core circuit 13. On the contrary, with regard to the flip chip BGA package 40, the power rings 50a, 50b, 50c corresponding to the input/output circuits 44a, 44b, 44c are positioned outside the power ring 50d corresponding to the core circuit 43. In other words, each of the wire bonding BGA package 10 and the flip chip BGA package 40, as shown in FIG. 2 and FIG. 5, has a unique power ballout assignment. That is, when the dies with the same function are packaged by different packaging methods, two categories of BGA packages (the wire bonding BGA package 10 and the flip chip BGA package 40) correspond to different power ballout assignments. Because the power ballout assignments are not compatible with each other, circuit boards with different circuit layouts have to be adopted for respectively mounting the wire bonding BGA package 10 and the flip chip BGA package 40. Suppose that the packaging method suddenly alters. For example, the die is packaged to form the flip chip BGA package 40 instead of the wire bonding BGA package 10. Because the power ballout assignment of the wire bonding BGA package 10 is not compatible with that of the flip chip BGA package 40, the flip chip BGA package 40, therefore, cannot be installed on the circuit board that is originally designed to support the power ballout assignment of the wire bonding BGA package 10. If the manufacturer of the circuit board modifies layout design of the circuit board to meet requirement of the flip chip BGA package 40, the production cost of the circuit boards certainly increases. On the other hand, if the manufacturer of the circuit board refuses to alter original circuit layout suitable for the wire bonding BGA package 10, the flip chip BGA packages 40 are unmarketable so that corresponding inventory is increased. Therefore, the total production cost of the BGA packages increases.